Portable consumer electronic devices continue to add features and capabilities to provide consumers better access to the growing availability of digital content. Consumers increasingly expect access to digital content wherever they go. The portability of digital content has created a demand for devices with increased functionality, reduced size, and extended battery life. Devices with greater functionality, however, often consume more power, reducing battery life.
Portable consumer electronic system designers and chip designers utilize a combination of hardware and software functionality to reduce the overall power consumption of these devices. Often, power consumption is separated into two states: active and standby. In the active state, the device operates at a specific frequency or multiple frequencies to perform a task. During the active state, power consumption can be separated into dynamic, or switching, power, and leakage power. Dynamic power results from transistors switching state, while leakage power is static, influenced by supply voltage, transistor switching threshold voltage, and temperature.
In 130 nm process geometries, dynamic power is typically the dominant component of active power. However, in 90 nm, 65 nm, and smaller process geometries, the leakage power component can be comparable to or greater than the dynamic power component. Smaller process geometries allow chips to run at the same frequency but with reduced voltage, thereby reducing dynamic power. In addition, the voltage threshold of the transistor are similarly reduced relative to the supply voltage. However, the aforementioned factors contributing to the reduction of dynamic power conversely cause an exponential increase in leakage power.
Leakage power, in addition to contributing to increased active power consumption, also increases standby power consumption, further reducing battery life. Particularly, in battery operated devices with a high ratio of standby to active operation, leakage current is the primary factor in determining overall battery life. In a standby mode, a device enters a sleep state by turning off all non-essential operations. However, during standby mode, essential functions, such as state retention logic, remain active.
Chip designers have implemented several techniques to reduce leakage power during standby mode operation. For example, some techniques use clock gating, multi-voltage threshold based designs, dynamic voltage threshold control, and power gating. Power gating, in particular, has become a common method of leakage power reduction used in low-power chip designs. In general, power gating involves disconnecting or reducing the power supply voltage to specific circuits. By isolating the power supply from these circuits, their respective leakage current paths are eliminated.
Generally speaking, low-power chip designs often isolate or disconnect the real or primary power supplies from particular circuits using a power gate device comprised of high-threshold transistors. The power gate device can be placed as a header, between the real power supply and the digital logic or, alternatively, as a footer between the digital logic and the return ground. Using high-threshold transistors reduces standby leakage current when the power gate device is off. The remaining logic, which often includes data registers comprised of master-slave flip flops, uses low-threshold devices to increase data throughput during active mode operation. During standby mode operation, the state of the of the master-salve flip flop must be retained to provide the processor a valid starting point to resume operations upon waking up. Applying power gating to data registers, however, prevents the master-slave flip flop from retaining the state information essential to resume normal operation when the device leaves the idle state or standby mode. As a result, an additional circuit, called a retention latch or balloon latch, is often coupled to the master-slave flip-flop to provide state retention during standby mode.
The retention latch is often comprised of high-threshold transistors used to reduce leakage current. In active operation, the power gate switch is on and the low-threshold master-slave flip flop samples its data input based on the appropriate clock edge, passing the sampled value to its output. The output of the master-slave flip flop is coupled to the input of the balloon latch. As the flip flop continuously samples and passes those values to its output, the value stored in the balloon latch changes accordingly. Prior to initiating standby mode, the real power supply is decoupled from the low-threshold power gate by switching the power gate off. As previously mentioned, a low-threshold power gate, used as a header, isolates the idle logic from the power supply during standby mode, eliminating the leakage path. The balloon latch remains coupled to the real power supply, maintaining the previous state value. When the active mode is resumed, the real power supply is recoupled to the master-slave flip flop by switching the power gate switch on. The processor resumes operation based on the value stored in the balloon latch.
Retention latches do, however, increase the circuit area and consume additional leakage power during standby and active operation. For some portable electronic devices, reduced device size is often an important feature. Minimal active and standby mode power consumption, similarly, is also a critical feature for these types of devices. For devices that have a high ratio of standby mode to active mode operation, such as smart phones and media players, reducing standby mode power consumption is essential to extending battery life. What is needed is a state-retentive flip flop with reduced area that minimizes leakage power consumption during standby mode operation.